The present invention relates to an electrically erasable and programmable nonvolatile semiconductor memory device.
In general, in an electrically erasable and programmable read only memory (EEPROM), it is known that data is programmed or erased by injecting electrons into a floating gate or emitting electrons from the floating gate through a thin silicon oxide film. For example, as shown in FIG. 1, a memory cell which is used in such a kind of EEPROM comprises: an MOS transistor 1 of a double gate structure which has a floating gate and a control gate and is used to store the data; and a selection MOS transistor 2 of an enhancement type connected in series with MOS transistor 1. The drain of selection MOS transistor 2 is connected to a column line 3. The source of MOS transistor 1 for data storage is, for example, grounded.
FIGS. 2A and 2B show an example of a memory cell device having such a constitution. FIG. 2A shows a plane pattern of the memory cell. FIG. 2B shows a cross sectional structure taken along the line I-I in FIG. 2A. In FIGS. 2A and 2B, n.sup.+ -type semiconductor regions 12, 13, and 14 are separately formed in the surface area of a p-type silicon semiconductor substrate 11. Region 12 constitutes the wiring of column line 3 and the drain of selection MOS transistor 2. Region 13 constitutes the source of selection MOS transistor 2 and the drain of data storage MOS transistor 1. Further, region 14 constitutes the source of MOS transistor 1. A gate electrode 15 of MOS transistor 2 is constituted by a polycrystalline silicon layer doped with impurities and having a low resistance, and is formed over substrate 11 between regions 12 and 13 through a gate insulating film (not shown) so as to be elongated in the lateral direction. A floating gate electrode 16 of MOS transistor 1 which is constituted by a polycrystalline silicon layer doped with impurities and having a low resistance and which is held in an electrically floating condition is formed over substrate 11, between regions 13 and 14, through a gate insulating film (not shown). Further, a control gate electrode 17 of MOS transistor 1 which is constituted by a polycrystalline silicon layer, doped with impurities and having a low resistance, is formed over floating gate electrode 16 between regions 13 and 14, through a gate insulating film (not shown), so as to be elongated in the lateral direction. On the other hand, a projecting portion 13A of n.sup.+ -type semiconductor region 13 and a projecting portion 16A of floating gate electrode 16 overlap through a thin insulating film 18 of about 100A..degree.
In the memory cell device having such a structure as shown in FIGS. 2A and 2B, to program data by injecting electrons into floating gate electrode 16 of transistor 1, control gate electrode 17 is set to a high potential, e.g., +20V. Thus, the potential of floating gate electrode 16 is raised by the capacitive coupling between the control gate and floating gate, the electric field between floating gate electrode 16 and n.sup.+ -type semiconductor region 13 increases, and the electrons are injected into floating gate electrode 16 through thin insulating film 18. Therefore, the threshold voltage of MOS transistor 1 increases.
On the contrary, to erase the data, namely, to release the electrons captured in floating gate electrode 16, control gate electrode 17 is set to a low potential, for example, a ground potential of 0 V and at the same time, gate electrode 15 and n.sup.+ -type semiconductor region 12 of MOS transistor 2 are set to high potentials. Therefore, MOS transistor 2 is turned on, n.sup.+ -type semiconductor region 13 becomes high potential, and the electric field between projecting portion 16A of floating gate electrode 16 and projecting portion 13A of n.sup.+ -type semiconductor region 13 increases in the direction opposite to that when the data is programmed. Consequently, the electrons are emitted from floating gate electrode 16 through thin insulating film 18 and the threshold voltage of MOS transistor 1 decreases.
FIG. 3 is a graph of characteristic curves showing the relation between a control gate voltage VCG and a drain current ID of MOS transistor 1 in the memory cell shown in FIG. 1. In the graph, a curve 21 shows the characteristic of the initial state in which the data is not programmed. Curve 22 shows the characteristic after the data was programmed by injecting the electrons into the floating gate electrode. A curve 23 shows the characteristic after the data was erased by emitting the electrons from the floating gate electrode. In such a memory cell, by programming or erasing the data, the MOS transistor having the initial characteristic of curve 21 in FIG. 3 may be changed to have the characteristic of curve 22 or 23.
FIG. 4 shows a memory cell array which is constituted by arranging the foregoing conventional EEPROM cells in a matrix form. Namely, a plurality of EEPROM cells MC-11 to MC-MN are arranged in a matrix form in the row and column directions. The gate electrodes of MOS transistors 2 of a plurality of memory cells which lie on the same row among memory cells MC-11 to MC-MN are commonly connected to a corresponding one of a plurality of row lines 31-1 to 31-M. Further, the control gate electrodes of MOS transistors 1 of a plurality of memory cells which lie on the same row are commonly connected to a corresponding one of a plurality of control gate lines 32-1 to 32-M. The drains of transistors 2 of a plurality of memory cells which lie on the same column are commonly connected to a corresponding one of a plurality of column lines 33-1 to 33-N.
The data programming and erasing operations of the memory having such a memory cell array will now be described with reference to a timing chart in FIG. 5. It is now assumed that, for example, the data is programmed into memory cell MC-11, connected to row line 31-1 and column line 33-1, and that the data is erased from memory cell MC-12, connected to row line 31-1 and column line 33-2. First, as shown in FIG. 5, row line 31-1 is selected and set to a high potential. Simultaneously, control gate line 32-1 of the row corresponding to row line 31-1 is also set to a high potential. At this time, two column lines 33-1 and 33-2 are set to a low potential, irrespective of the data programming and erasing operations. In two memory cells, MC-11 and MC-12 in this case, the electrons, are injected into the floating gate electrodes, as mentioned above. Thereafter, control gate line 32-1 is returned to a low potential and column line 33-2 is further set to a high potential. Thus, in memory cell MC-12, connected to row line 31-1 and column line 33-2, the electrons are emitted from the floating gate electrode, as mentioned above, and the data is erased. In this manner, the data is programmed and erased in memory cells MC-11 and MC-12, respectively.
However, as will be obvious from the above description, in the memory cell array using the conventional EEPROM cells, both the data programming period and the data erasing period are separately necessary. In other words, the electrons cannot be simultaneously injected and emitted into and from the floating gate electrodes of different memory cells, so that there is a drawback, in that it takes a long time to rewrite the data.
In addition, in such a memory cell, the charging and discharging of the floating gate is accomplished by Flowler-Nordheim tunneling of electron across the thin insulating film 18, thereby allowing the data to be programmed or erased. Therefore, the electrons pass through insulating film 18 (FIG. 2B) and are trapped into insulating film 18, causing the insulation performance of insulating film 18 to deteriorate. Therefore, in the ordinary EEPROM, the number of data rewriting times of only about 10.sup.4 to 10.sup.5 is assured. However, according to the memory cells of the conventional structure, when arranged in a matrix form to constitute an integrated circuit, the control gate electrodes (gates 17 in FIGS. 2A and 2B) need to be commonly used for every row line. Therefore, in the case of programming and erasing the data, the data will be also once programmed into the memory cell from which the data should be erased, by releasing the electrons therefrom. Namely, the process to inject the electrons before the electrons are emitted certainly exists. Therefore, in the worst case, when the data is once rewritten, the electrons pass through insulating film 18 twice. If the number of times of passage of the electrons in insulating film 18 can be reduced to one, the number of writable times of the data will be doubled.